Technology File

The technology file contains process specific parameters such as layer thicknesses and the sheet resistance of the various layers. There are two sample technology files included for reference. These technology files describe a generic CMOS and BiCMOS process. Using the comments in these files you should be able to set up your own technology file pretty quickly.

Let's use the generic CMOS process as an example. Below is the technology file for such a CMOS process. The cross-section of the various substrate layers in shown in the figure below. The technology is divided into sub-sections. The first sub-section begins with the <chip> statement. The first two lines in the chip section define the chip x and y dimensions. For best results set the area to contain about four times the area of the layout. For instance, if you are simulating a spiral inductor of dimention 200x200, then use a 400x400 chip size.

The next two parameters are the 2D FFT sizes. There is a relation between the chip size and the FFT size that determines simulation accuracy. The smallest panel of charge is a rectangle of dimension chipx/fftx by chipy/ffty. As a guideline, pick the FFT size so that at least one panel of charge can fit between all the metal structures residing in the layout. For instance, for a square spiral with spacing of 2 microns, aim for chip/FFT less than or equal to 2 microns. Generally, the larger the FFT size, the more memory required by the simulator. Thus the smallest FFT size that gives sufficient accuracy is optimal. The minimum recommended FFT size is 128x128. The TechFile is the name of the technology file that you choose. The TechPath is where binary data files will be stored. These files can be large (depending on the FFT size) and thus a local fast access point is optimal. Avoid putting these files on a slow NFS mounted directory. If you use the /tmp directory, keep in mind that you may want to keep these files across sessions since for a given fixed technology file, the binary data files only need to be generated once.

<chip>
        chipx = 512    ; dimensions of the chip in x direction in microns
        chipy = 512    ; dimensions of the chip in y direction
        fftx = 256     ; x-fft size (must be a power of 2)
        ffty = 256     ; y-fft size
        TechFile = sample.tek   ; the name of this file
        TechPath = /home/niknejad/tekf ; the pathname of the data files
        freq = .1

<layer> 0     ; Bulk Substrate

        rho = .1                ; Resistivity:  ohm-cm
        t   = 400               ; Thickness:  microns
        eps = 11.9              ; Permitivity:  relative

<layer> 1     ; Epi Layer 

        rho = 15                ; ohm-cm
        t = 1                   ; microns
        eps = 11.9              ; relative

<layer> 2     ; Oxide Layer

        rho = 1e10              ; ohm-cm 
        t = 50                  ; microns
        eps = 4                 ; relative

<metal>  0    ; Substrate Contact Layer

        layer = 1               ; Epi Layer 
        rsh = 30                ; Sheet Resistance Milli-Ohms/Square
        t = 0.1                 ; Metal Thickness (microns)
        d =  .5                 ; Distance from bottom of layer (microns)
        name = msub             ; name used in ASITIC
        color = yellow          ; color in ASITIC

<via> 0       ; metal 1 to substrate

        top = 1                 ; via connects up to this metal layer
        bottom = 0              ; via connects down to this metal layer
        r = 5                   ; resistance per via
        width = .4              ; width of via
        space = 1.3             ; minimum spacing between vias
        overplot1 = .3          ; minimum dist to substrate metal 
        overplot2 = .3          ; minimum dist to metal 1
        name = via0             ; name in ASITIC
        color = purple          ; color in ASITIC

<metal> 1     ; metal layer 1  

        layer = 2
        rsh = 50
        t = 1
        d =  1.62
        name = m1
        color = red

<via> 1       ; metal 1 to metal 2

        top = 2
        bottom = 1
        r = 4
        width = .5
        space = 1.5
        overplot1 = .4         ; to substrate metal 
        overplot2 = .4         ; to metal 1
        name = via1
        color = white

<metal> 2     ; metal 2

        layer = 2 
        rsh =   32
        t   = 1.3
        d = 2.74
        name = m2
        color = blue

Next, the <layer> statements define the various dielectric and substrate layers. A conducting substrate layer is specified by stating its resistivity in ohm-cm. A dielectric layer can be modeled as an equivalent resistivity according to the dielectric loss tangent. The thickness is specified in microns. The relative permitivity is unitless. Notice that the substrate layers are defined from bottom up. In other words, the order is important. Thus the bulk layer is listed first, followed by the epi, and finally followed by the oxide layer. Note also that the air and ground layers do not need to be explicitly defined as they are implicitly in the boundary conditions. See the section boundary conditions for more details.

The conducting metal layers are defined in the <metal> sections. Each metal layer belongs to a specific layer specified with the layer identification. Most metal layers will be defined in non-conducting oxide layers. This is true for the last two metal layers in the technology file above, but notice the first metal layer, named MSUB, actually resides in the epi layer. This is because this metal layer is used to ground the substrate (a substrate tap). This can be an important effect to model in simulation as it will affect the substrate current, isolation, and loss (see the section on boundary conditions ). The sheet resistance of the metal layers is specified in milli-Ohms/Square along with the metal thickness. The z-coordinate of the bottom of the metal layer is specified with d = xx where d is the distance in microns from the bottom of the substrate layer to the bottom of the metal layer. The name that you give the metal layer will be recognized in ASITIC so use an easy to remember alias such as M1. The color you specify will also be used in ASITIC to distinguish the metal layers. Notice that the order is important here as well. The metal layers are listed from bottom up and this is how they will be drawn in ASITIC.

You can also define optional vias to make connections from metal layer to metal layer. Note that vias are totally optional and usually play a minor role in determining the characteristics of a device. On the other hand, one can create multi-layer devices, or symmetric center-tapped inductors, with many via connections in series with the device. In these situations the inclusion of vias is necessary. Via layers are added in the <via> sections. The top and bottom sections define the metal connectivity of the via. Note that the numbers correspond to the numbers used in the <metal> sections. The resistance per via is specified by r = xx. Note that while a single via may have a relatively large resistance, many such vias are usually employed in parallel to lower the contact resistance. Thus it is essential for ASITIC to know the via dimensions and minimum spacings. These numbers come from the design rules of the process. The overplot distances are the minimum distances between the edge of the via and the metal edges (bottom metal and top metal).

Boundary Conditions

There are two relavent boundary condtions in ASITIC. While solving for the inductance matrix, the partial inductance matrix is computed assuming that each segment resides in an unbounded lossless medium. Thus, any induced eddy currents in conducting structures must be included explicitly in the computation. The eddy flag turns on the eddy-current calculation engine which includes substrate eddy currents. Eddy currents in the metalization is computed approximately by discretizing the thickness and width of each conductor. In the capacitance matrix computation, ASITIC assumes that the back-plane of the lowest substrate layer is a perfect ground at zero potential. The top layer is assumed to interface with air. The side-walls boundary condition is that there is no field component penetrating the walls. These boundary conditions give reasonably good results without requiring a very large 'box' (chip size). For instance, many EM simulators assume a short on the side walls as well. This forces one to use a very large box to place the box walls sufficiently far from the device such that the boundary conditions do not effect the near field (although the far field radition will be very dependent on these boundary conditions, the device is much smaller than the wavelength and radiative effects are ignored).

The assumption that the back of the chip is connected to a good ground may not be strictly true. For instance, the chip might be glued with a non-conductive material to the package. Furthermore, many inexpensive packages do not have an opening to allow an ohmic contact to be made with the lead frame, and thus the chip is floating. In these cases, you can simulate this effect by adding another substrate layer below your bulk substrate to model the interface. You can give it very low conductivity (rho=1e10) and very low permitivity (to prevent substantial displacement current from grounding the substrate). Also, to get meaningful simulations results, you need to add a third port to your device, where you define your ground connection. This is done through the substrate contact layer in the technology file or using a ground shield.

Binary FFT Data Files

Internally, ASITIC translates your technology file into a form suitable for efficient numerical computation. This data is stored in a series of binary data files (for each frequency point). This computation only needs to be performed once for a fixed technology file. ASITIC automatically detects when the technology file and the binary data file go out of synchronization and will re-generate the binary files as needed.

The memory requirements place a limit on the FFT size you choose in the technology file. Generally, it is advisable that the FFT data fit into memory to avoid lengthy swaps. For Nmetal layers and an FFTsizexxFFTsizey size FFTs, each frequency point requires (Nmetal+1)xNmetal x FFTsizex x FFTsizey x sizeof(double) bytes of memory. For instance, a process with 3 metal layers and a 128x128 size FFT and a machine with sizeof(double)=8 requires 786 kbytes per frequency point. On the other hand, the same process with a 512x512 FFT sizes requires 12 Mbytes of memory. For a workstation with 128 Mbytes of RAM these numbers are very reasonable.