ASITIC Documentation: Grackle Release
|Command Reference||Environmental Variables||Installation||Technology File||Quickstart||Sample Sessions||FAQ|
ASITIC is an interactive CAD tool that aids RF/microwave and high speed digital engineers to analyze, model, and optimize passive and interconnect metal structures residing on a lossy conductive substrate. This includes inductors, transformers, capacitors, transmission lines, interconnect, and substrate coupling analysis. ASITIC allows the circuit designer to plan and optimize the layout of a chip in the presence of magnetic and electrical interaction and coupling through the substrate and oxide layers of the IC. Process engineers can also employ ASITIC to assess the effect of process changes to the quality of passive devices and isolation.
ASITIC works with a mini technology file that describes the substrate and metal layers of the process. ASITIC is fairly general, allowing any number of substrate layers or metal layers to reside in the technology. Typical IC processes utilize three to four substrate layers (bulk, epi, oxide, passivation) and three to six metal layers.
ASITIC can output s-parameters for inductors/transformers/bond pads/capacitors. ASITIC can also be used to obtain broadband circuit models of the structures which can be used in SPICE simulation. The final layout of the design can be saved as a CIF file and imported into layout tools for final fabrication.